1. Field of the Invention
The present invention relates to a data transfer system for transferring data between two processors, i.e., two central processing units (CPUs).
2. Description of the Related Art
A prior art inter-processor data transfer system of the type under consideration includes two pairs of first-in first-out memories (FIFOs) are arranged between a pair of CPUs and data are written and read in the FIFOs at the operating speeds of the respective processors (see JP-A-56-135261). This will be explained later in detail.
In the above-described prior art data transfer system, however, a very large circuit is required for the system as a whole.
Also, it takes time for each of the CPUs to find out if the partner CPU received the data it sent out. Further, if one of the CPUs wants specific data of the other CPU and requested the latter CPU to send the specific data by way of a related FIFO, the data that the former CPU receives by way of a related FIFO may not be the data it wants.